The present invention relates to an FET (which is the abbreviation of a "field effect transistor") and contemplates to ensure a high speed of the FET by the self-alignment among component elements such as electrodes.
A major portion of an FET, which has its substrate made of GaAs, i.e., a chemical compound semiconductor, is shown in section in FIG. 1. This FET is operated by controlling the electric current, which flows through an n-type channel layer 4 formed between two ohmic electrodes formed on the surface of a semi-insulating semiconductor substrate 1, i.e., between a source electrode 2 and a drain electrode 3, by a signal input which is applied to a gate electrode 5. Its threshold voltage is controlled by changing the thickness of a depletion layer 6, which is formed below the gate electrode 5. Below the ohmic electrodes 2 and 3, moreover, there are formed n.sup.+ -type layers 7 and 8 which are generally intended to reduce the ohmic resistance.
The operating speed of that FET is determined mainly by the transconductance and the resistance between the source and the drain. In other words, the operating speed increases with increasing transconductance and with decreasing drain resistance. The transconductance is substantially in inverse proportion to a gate length 9 whereas the aforementioned resistance becomes the lower as both a channel length 10 and a gap 11 between the source and the drain are the smaller. In other words, it is necessary to reduce the lengths of these 9,10 and 11 to make the switching speed of the FET faster.
If these component elements such as the electrodes are prepared by the photo-lithographic process, these lengths are restricted by the precision of the process. Therefore, a variety of self-alignment processes have been developed as a method for patterning these component elements without resorting to a lithographic process.
However, any fabricating method capable of sufficiently achieving the practical objects has not been found yet.
Next, the problems accompanied with the prior art will be specifically pointed out.
FIG. 2 and FIGS. 3a to 3c show the examples of the FETs which are fabricated by the prior self-alignment processes.
In the example of the FET shown in FIG. 2, after the channel layer 6 has been formed, an ion implantation for forming n.sup.+ -type layers 7' and 8' is conducted by using a gate electrode 5' as a mask thereby to effect the self-alignment between the gate electrode 5' and the n.sup.+ -type layers 7' and 8'. In this way, the gap between the two n.sup.+ -type layers, i.e., a channel length 10' can be shortened.
However, this FET has a problem that a breakdown voltage between the gate electrode 5' and the n.sup.+ -type layers (7' and 8') is liable to be deteriorated. As the self-alignment cannot be effected between the source and drain 2 and 3 and the gate electrode, moreover, a source-drain gap 11' can't be shortened.
Another example of the FET is shown in FIGS. 3a to 3c. In this example, as shown in FIG. 3a, Si ions 16 for forming n.sup.+ -type layers 15 and 15' are implanted, as indicated at 16, through a Si.sub.3 N.sub.4 layer 14 acting as a protective film of the substrate 1 by using a SiO.sub.2 film 13 as a mask, which is formed in an overhung shape on a photo-resist film 12.
Next, after SiO.sub.2 films 17 and 17' have been formed as coatings all over the surface by a sputtering process, as shown in FIG. 3b, the SiO.sub.2 films 13 and 17' are lifted off by dissolving the photo-resist film 12 thereby to make the reversal of the mask, that is, the interchange of the covered portion of the GaAs surface from the gate electrode portion into another portion. After the n.sup.+ -type layers have been activated by an annealing process at a temperature higher than 800.degree. C., then, the Si.sub.3 N.sub.4 at the aperture of the SiO.sub.2 film is removed. As shown in FIG. 3c, furthermore, a gate electrode 18 is fabricated at the aperture by the use of the lithographic process. On the other hand, source and drain electrodes 19 and 20 are formed by the lithographic process of the prior art.
In this way, the n.sup.+ -type layers 15 and 15' and the gate electrode 18 can be formed and separated from each other at the distance corresponding to the overhang length of the SiO.sub.2 film 13. Even by this process, however, it is still impossible to effect the self-alignment between the gate electrode 18 and the source and drain 19 and 20. This is because, although the source and the drain have to be formed prior to the mask reversal and the anneal of n.sup.+ layers in order to make the self-alignment, the metal used for the source and drain electrodes is thermally deteriorated at the annealing temperature (higher than 800.degree. C.). And because of the presence of the photo-resist film 12, the annealing process cannot be conducted before coating the source and the drain. Therefore, a source-drain gap 21 (corresponding to the gap 11 of FIG. 1) cannot be narrowed.
Moreover, the positioning of an upper portion 18' of the gate electrode 18 cannot be made without photo-lithography so that its position not only becomes inaccurate but also it has to be made wider than the width of the original photo-resist film 12. As shown in FIG. 3c, therefore, that upper portion 18' is piled up on the SiO.sub.2 film so that it is difficult to fabricate these elements in planar form. At the same time, since the n.sup.+ -type layer 15 and the gate electrode 18 overlie each other through the insulating film 17 so that the overlapped region acts as a capacitor, an input capacitance between the source electrode 19 and the gate electrode 18 is increased to deteriorate the characteristics of the FET.